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Logisim-evolution

logisim-evolution developers · logisim-evolution.logisim-evolution

Digital logic design tool and simulator

winget install --id logisim-evolution.logisim-evolution --exact --source winget

Latest 4.0.0

Release Notes
  • v4.0.0 (2025-09-07)
    • Updated VHDL and created Verilog generator for RAM component with byte-enables
    • Added VHDL and Verilog for the RAM component with line-enables
    • fixed clasic appearance shift-register bug
    • Added automatic custom Logisim library loading at startup.
      • Created unit tests for loading custom Logisim libraries at startup.
      • Updated documentation for the automatic loading of custom Logisim libraries.
    • New take on project export/import. A zip-file is generated which can include a user provided "README.md".
    • Added Telnet component.
    • Added Metal graphics acceleration option.
    • Added option to hide/show toolbar
    • Improved drawing appearance.
      • Fixed TTY appearance bug while changing various zoom levels.
      • Corrected appearance of NOT gates in TikZ/SVG image export.
      • Corrected disjoint corners in arrow-style Pins.
      • Improved output of rectangles with rounded corners in TikZ image export.
    • Fixed Undo/Redo issues.
    • Fixed Power-on-Reset propagation issue.
    • Redesigned simulation engine to fix synchronization issues and increase speed.
      • Fixed synchronization and efficiency issues in wires and propagation.
      • Fixed synchronization and efficiency issues in propagation listeners.
      • Limited redraws to about 20 frames per second to reduce overhead.
      • Allows users to choose a simulation queue, which changes the efficiency of the simulator depending on circuit design.
    • Simplified Type and Behavior attributes of Pins.
      • This change will break circuits with input pins that need to pull floating values to 0 but do not have the Pull Down setting. To fix it, set the Behavior attribute to Pull Down.
      • Updated Pin documentation.
    • Subcircuits with clock input(s) are now drawn with a clock symbol.
    • Added TTL 74194: 4-bit bidirectional universal shift register.
    • Improved the English, French, and German localization. Smaller fixes were done to the other languages as well.

Installer type: wix

Architecture Scope Download SHA256
x64 — Download 80F87330EE7B4BC55BCB58EF10DFCDACBA12C47C74BB8128F2F1CB9D86EC6815
arm64 — Download DDDBF74C8C0D5681B8266F4DC5D2F58536F0B59A614DC00EA5F5A622E2B2B5F8

Details

Homepage
https://github.com/logisim-evolution/logisim-evolution
License
GPL-3.0
Publisher
logisim-evolution developers
Support
https://github.com/logisim-evolution/logisim-evolution/issues

Tags

circuitdiagramdigitaleducationjavalogiclogisimsimulatorverilogvhdl

Older versions (2)

3.9.0
Architecture Scope Download SHA256
x64 — Download 6E2FEFE5BEEB2CAFBCDA310EEF8550E7CCEF48397156E2E15C3F8F13576EE5F9
arm64 — Download 7742953D87612C62CE7C721F33724F75C31996C223C98765DB6E52634DCBE740
3.7.2
Architecture Scope Download SHA256
x64 — Download AA02480D298FF06CBFCD43C97AEAD0D053E809E7FDC10C8E5E0A9C9213BDB914